In increasing the data throughput rate for bussed systems, such as processors, memories, personal computer, computer systems, the use of low signal level busses has been proposed. By reducing the high output voltage level standard for a particular bus, the switching time is improved because the voltage swing is limited to a few hundred millivolts, as opposed to the older bus standards which required as many as 5 volts to transition from a low voltage state to a high voltage state. Two of the developing bus standards which adopt this approach are the Gunning transceiver level (GTL) bus, and the CTL or CMOS transceiver level bus. Each of these busses defines the output voltage for the high state as being around 1 volt, with some variation, and the low state being around zero volts. The bus specifications of these proposed busses typically require that they be open-collector or open-drain type busses, that is the bus is pulled up to the high output state by an external R-C network. The output drivers must then overcome these pullup circuits to assert a low voltage on the bus.
The problem in implementing low voltage level signal busses like these proposed busses using the circuits of the prior art is that noise produced by the output driving devices can cause erroneous results in the signal receiving devices, because the available noise margins have been greatly reduced. If the device driving the bus switches quickly from a high state, that is letting the bus rise to a one volt signal, to a low state, that is outputting a signal of approximately zero volts, ringing may occur on the bus. This ringing can cause the receiving devices to erroneously input a transient as true data, that is the ring can look like a zero state on the bus followed by a high state, then a second zero state. The ringing is caused because the transition from the high state to the low state by the output driver is happening too sharply. This is often stated as the slew rate of the output driver device is too low.
Conventional approaches to this problem include adding a slew rate capacitor at the gate of the driving transistor. FIG. 1 depicts a prior art circuit using this approach. Output buffer 1 includes an input for receiving the data to be transmitted on the bus, an output driving transistor, typically an open drain N channel MOSFET transistor, as shown here, although P channel or bipolar devices can be substituted; an output terminal coupled to the drain of the driving transistor 5. A capacitance 3, which can be provided in various ways that are obvious to one skilled in the art, is coupled to the gate input of the output transistor 5.
In operation, assume first that the signal at the input terminal `IN` in FIG. 1 is low. The output driver transistor 5 is then shut off, and the output terminal is allowed to pull up to the high voltage state. Now a transition occurs at the input terminal `IN`, and a high voltage is present. The voltage at the gate of transistor 5 remains low initially. As capacitor 3 is charged to the high state, the gate voltage will eventually reach a point where the voltage Vgs, that is between the gate and the source of transistor 5, exceeds the turn on or threshold voltage of the output driver and the output driver transistor begins pulling the voltage at the output terminal down towards ground. The capacitor 3 has in fact slowed the rate of transition of the output driver gate 5. With an external load of 25 ohms and 30 pF, a circuit like that in FIG. 1 has been shown to take 0.5 nanoseconds to swing the output from 1.1 volts to 0.6 volts, or 1 Volt/nanosecond. This fast transition rate will produce significant ground spikes within an integrated circuit including the output driver, and will also produce large reflections on the bus, crosstalk between data lines, and noise on the bus. Also, this approach fails to provide the rapid transition time from an input transition to an output transition, that is switching time, required by current state of the art systems, because the capacitance at the gate of the output driver must be charged and discharged before the output driving transistor begins to switch. The result is an output buffer that has a somewhat controller slew rate but is too slow overall to meet the specifications for these newly proposed high speed busses. Also, once the input signal at the `IN` terminal again transitions, now to a low input state, the capacitor 3 must discharge into the gate of the transistor 5 before the transistor 5 will stop driving the bus low. So the rise time for the output driver 5 is also affected by the capacitor 3, which further slows the circuit without positively impacting the slew rate.
The proposed high speed bus standards require output driving circuitry that has a fast transition time and a tightly controlled slew rate, so that switching noise does not exceed the reduced noise margins. The prior art circuitry cannot provide a solution that meets the requirements of these proposed busses. A need for a circuit having fast switching speed and improved slew control and low noise characteristics thus exists.